EASY FPGA Finite State Machine
FPGA Project 09
This Verilog tutorial will help You to create an EASY FPGA Finite State Machine!
At the end of this Verilog project for beginners you will be able to display the “EASY FPGA” pattern on the 7 segment displays from your FPGA board.
Part 1 Verilog tutorial and Modelsim simulation
This practical Verilog tutorial for beginners will show you the following:
- How to design a custom 7 segment Decoder in Verilog
- How to design a Verilog EASY FPGA Finite State Machine for FPGA
- How to implement a Verilog testbench for the EASY FPGA module and a Modelsim simulation using
Part2 – FPGA programming with Intel Quartus Lite
This FPGA programming project for beginners will show you the following:
- How to Synthesize the EASY FPGA project in Intel Quartus
- How the Verilog code translates into a digital circuit using the RTL Viewer
- How the Quartus State Machine Viewer creates a state transitions diagram
- How to use pipelining and reset type to improve your circuit timing and increase the maxim frequency
- How to program the FPGA and demo trial using the DE1-SoC Cyclone5 development board
I hope you enjoyed this Verilog FPGA tutorial 😊
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