FACEBOOK GROUP RULES
USE ENGLISH LANGUAGE ONLY
To make sure all members of the group understand you, please use only the English language. You don’t need to have perfect English spelling skills, but you need to write in such a way others understand you. You can always use google translate if you need extra help 😉 .
SHARE YOUR VERILOG QUESTIONS
Feel free to share your Verilog design and Verification questions with the group. Explain what engineering problems you encounter and we’ll help you solve them using Verilog. It helps a lot to post your Verilog code and simulation results to get a viable solution from the other members of the group.
NO PROMOTIONS OR ADVERTISING
Give more than you take in this group. Self-promotion, spam and irrelevant links aren’t allowed.
It is prohibited to post links with the sole intent to promote your content / courses / companies that you are affiliated with for commercial purposes. It is generally prohibited to post job listings, advertising services, or requesting work in the group.
Exceptions to the above are pre-approved posts. Contact the group admin (Ovidiu Plugariu) to ask for approval before posting such content.
BE KIND AND CURTEOUS
We’re all in this together to create a Welcoming environment. Let’s treat everyone with respect. Healthy debates are natural, but kindness is required. Don’t launch personal attacks on other members. You may criticize the proposed ideas and arguments, but never the people behind them.
Make sure everyone feels safe. Bullying of any kind isn’t allowed, and degrading comments about things like race, religion, culture, sexual orientation, gender or identity will not be tolerated.
POST RELEVANT CONTENT
Posts should be at related to Verilog, FPGAs, ASICs, or digital logic design and functional verification. Discussions about non-technical subjects are welcome as long as they are remotely related to the mentioned subjects.
It is prohibited to ask for complete solutions to homework, exams, or employment skill tests. Although asking for help with specific parts when you are stuck and have tried to solve the problem is accepted.
Examples of subjects that are allowed:
- Workplace related matters
- Faculty projects related matters
- Career advice for the Digital Semiconductors industry
- Introducing yourself to the group
- Jokes and memes that are somewhat related to Verilog or FPGAs
- Scripting languages used in conjunction with VHDL or FPGA tools
- Talk about FPGA related hardware
Examples of subjects that are not allowed:
- Talk about VHDL that doesn’t involve Verilog / SystemVerilog somehow
- Talk about other programming languages which have no relevance to Verilog or FPGAs
- Other, completely unrelated content
