Hamming FPGA SECDED
FPGA Project 04
Project description
Hamming Codes are a class of error correction codes based on parity bits that can correct 1bit errors and detect 2bit errors when data is stored or even during transmission.
Let’s implement a Hamming code Single Error Correction Double Error Detection (SECDED) circuit using Verilog!
This practical Verilog tutorial for beginners will show you the following:
- How to design a Hamming encoder with parity bit (Hamming84 encoder)
- How to design a Hamming decoder with parity bit (Hamming84 decoder)
- How to design a Noise generation module – Design for Testability feature used to insert 1bit, 2bit and 3bit errors
- How to design a Priority encoder used to transform the Hamming syndrome one-hot value to a binary value
- How to design a 7Segment display used to show the current error position (the syndrome)
- How to design a Hamming SECDED module based on Hamming74 codes
- How to implement a self-checking testbench in Verilog and simulate the Design Under Test using Modelsim Student edition
Part 1 Verilog tutorial and Modelsim simulation
Part2 – FPGA programming with Intel Quartus Lite
This FPGA programming project for beginners will show you the following:
- How to create an Intel Quartus Project
- How to Synthesize a Verilog project with multiple files
- How to connect your design to the FPGA pins
- How to use a 7 segment display on an Intel/Altera FPGA board
- How to program the FPGA and demo trial using the DE1-SoC Cyclone5 development board
I hope you enjoyed this Verilog FPGA tutorial 😊
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