Free EASY FPGA Verilog course for beginners

Free EASY FPGA Verilog course for beginners

by | Jan 8, 2023 | Verilog Design

FREE EASY FPGA Verilog course for beginners

The EASY FPGA Verilog course for complete beginners is now online 🚀!

I know from my own experience and also from my students that Verilog and FPGAs can be very hard to understand when you are a complete beginner 😰. The steep learning curve combined with the fact that most procedural programming languages are easier to learn, make many Hardware Description Languages beginners focus their attention and future careers in other industries (read more here about the industry job shortage).

This course is the result of my 10 years of Hardware Description Languages experience as well as more than 5 years teaching beginners to interact with Verilog and FPGAs. When I was first starting out in this field I wish I had step-by-step Verilog design and simulation guidance for simple FPGA projects that can be implemented on most development boards.

This set of practical Verilog projects provide full video guidance and the downloadable resources you need to implement the first FPGA projects on your development board. Even if you don’t have a development board you can still simulate the projects and gain precious know-how about FPGA programming.

 

How is the FPGA Verilog course structured?

Each practical FPGA project has an article with two YouTube videos containing the following:

✅ Project overview and theoretical intro

✅ Verilog coding and Modelsim simulation (FREE link to Modelsim Intel FPGA Edition provided)

✅ FPGA project using Intel Quartus and FPGA demo using the DE1-SoC development board

✅ Downloadable resources so YOU can replicate the project on your development board.

Who this course is for ?

✅ Computer Science, Electrical & Computer Engineering (ECE), Telecommunications, and Microelectronics, students who want to learn Verilog for their projects and faculty assignments
✅ Electronics and Microelectronics hobbyists who want to learn the Verilog Hardware Description Language
✅ Beginners who aspire to a career as a Digital Design Engineer or a Functional Verification Engineer using Verilog
✅ Beginners in digital microelectronics and digital circuits design curious about the Verilog Hardware Description language

List of Verilog FPGA projects

✅ Switches to LEDs
✅ Multiplexer to LEDs
✅ Binary Adder to 7 Segment Display
✅ Hamming Single Error Correction Double Error Detection
✅ FPGA Blinky LED
✅ Pushbutton Counter with Debounce
✅ Linear Feedback Shift Register
✅ Verilog BCD Timer
✅ Finite State Machine
✅ Pulse Width Modulation (TODO)
✅ VGA Controller (TODO)

But just like the song says 🤘 “A little less conversation and a little more action!”…

Let’s start the EASY FPGA course and jumpstart your Verilog and FPGAs learning!

Master Verilog Write/Read File operations – Part1

Master Verilog Write/Read File operations – Part1

by | Apr 2, 2022 | Verilog Verification

This practical tutorial will show you how to perform simple Verilog write/read file operations and transfer data between testbench variables and Input / Output (IO) data files (it’s much easier than it sounds 😎).

Sometimes a Verilog design needs external stimulus – which is hard to generate inside a testbench, or the test scenario should be able to transfer read and write data outside the simulation environment. Some easy practical examples are:

  • A program memory for a CPU used as input file
  • Samples from an external sensor used for the module inputs
  • Passing the output results of our Digital Signal Processing module to another file to allow spectral analysis in Matlab
  • A list of expected values for the outputs

Verilog provides a set of standard system tasks and functions used for basic data reading and writing from and into files which allows you to:

  • Open files, then read the values and assign them to a local testbench variable
  • Open files, then write the values from a testbench variable to an external file
  • Close files

Verilog standard write/read file operations

Working with files in Verilog is straightforward. The flow has 3 easy steps:

  1. Open the file ($fopen)
  2. Write or read data to / from the file ($fdisplay, $fmonitor, $fstrobe, $fwrite, $fread)
  3. Close the file ($fclose)

How to open and close files in Verilog

$fopen(“data_in.txt”)  will return a 32bit unsigned integer called a Multi-channel descriptor (MCD) that has only one bit set to 1. If it was unsuccessful, it returns the value 0. Each $fopen will create a different MCD with a bit set to 1. You can open up to 30 MCDs because bit 0 is used by <stdout>, and bit 31 is reserved to 0.

$fclose(“data_in.txt”) will release the MCD value to be able to reuse it later in the testbench.

Verilog multi-channel descriptor In this simple Verilog example, we can see how to declare three Multi-Channel Descriptors to open three files with them.

We can see in the console how MCD1 and MCD2 get the decimal 2 and 4 values after using $fopen. The $fclose from line 16 will release the MCD value for MCD1, making it available for MCD3. Because there are only 30 possible MCD values, it is important to manage how many are actively used.

 

 

 

 

Verilog File Output: Writing to files

You can write data into files using a set of simple system tasks equivalent to the console display tasks: $fdisplay, $fwrite, $fmonitor, and $fstrobe.

A task can be called using a formatted message $fdisplay(MCD1, ” Speed = %4d km/h”, speed); or simply by passing the variable to be printed $fdisplay(MCD1, speed); .

Each task prints decimal values by default or through a variant that can print to binary, octal or hexadecimal. For example $fdisplay offers $fdisplayb(), $fdisplayo(), and $fdisplayh(). Let’s do a practical example to master them!

In this example, we are going to write the values of the temp and speed variables in speed.txt and temperature.txt. The test scenario is the following:

  • First, we declare the MCDs, the speed and temp variables, then we open the two files to start writing them. We start by writing both files with a generic text by using MCD3. Pro tip: By OR-ing some MCDs you can edit multiple files at the same time with the same text
  • Next, we change the values of the speed and temp variables and we print them separately in each file. After 1 time unit we change the values of the variables and print them again
  • In the end we write another generic message with MCD3 in both files and close all MCDs

You should get the following output results in speed.txt and temperature.txt:

 

Verilog File Input: Reading from files

If you want to read data from a file in Verilog, you can use the system tasks $readmemb or $readmemh. These tasks will get the data from the file (binary or hexadecimal) and pass it to a 1-D array of reg type vector. The syntax is intuitive as the task needs the input data file name, the destination vector, and optionally the start / stop address of the destination vector. Let’s analyze these by doing some quick examples!

First, create two files called data_in.bin and data_in.hex with the following content. Note that the files must be created at the same level where your simulator project is created (Modelsim in my case).

Next, you will create a Verilog file called file_read.v .

Verilog file read using $readmemb and $readmemh

The test scenario is the following:

  • We first declare two arrays that fit the bit width and depth of the binary values from the data_in files
  • At line 11, we use $readmemb to fill array1 with the binary patterns from data_in.bin
  • At line 14, we use $readmemh to fill the positions 0 to 3 with the HEX values from data_in.hex. Since the depth of array2 is 6, but we only load the first 4, array2[4:5] should remain noninitialized thus having the values 8’hXX
  • At line 16, we use two Verilog for loops to print the contents of the 1D arrays, and the simulator shows the values are the same as those from data_in files

Verilog File Input Data Format

$redmemh complex formatLet’s analyze a more complex data.txt format supported to load array1 using the command $readmemh(“data.txt”, array1):

  • Inline comments, empty lines and block comments are ignored
  • Line 2 is used to load addresses 0, 1, 2, and 3 with the HEX data 0xAB, 0x00, 0x99, and 0x21. Data for multiple addresses can be written on the same line
  • At line 5, we load array1[8] with 0xCD. The @ character is used to specify the start of an [address, data] pair. Since we skip directly from address 3 to address 8, all the array1[4:7] values will remain 8’hXX (noninitialized). Note that it is very important to write the address value in HEX
  • Lines 8 and 9 show that a pair [address, value] can be written on multiple lines. Note: this may be misleading and it not good practice

To test the memory file from above, please make a new Verilog file called file_read2.v with the following content:

$readmemh Verilog example

If you’d like to know more about advanced Verilog Enhanced C-Style file I/O methods, I recommend reading the article “Master Verilog Write/Read File operations – Part2” (work in progress).

 

I hope you enjoyed this practical Verilog tutorial. If you’d like to receive more articles like this, please join Ovisign’s newsletter or enter our Facebook community!

Want to easily master the basics of Verilog through practical examples?

Back in the day when I first started working with Hardware Description languages (Verilog and VHDL), I had tons of problems at every corner. The simulator wasn’t working, I didn’t know how to debug, I found it hard to understand how to translate from a digital circuit schematic to a Verilog code, and it was very hard to even write proper testbenches 😭😔… No wonder less than 2% of all engineers work in the Digital Semiconductors industry.

Luckily I didn’t quit, and after 20000h in Verilog/SystemVerilog for design and verification and a PhD in Electronics, I put together all the pieces of the puzzle I worked so hard to solve back in the days 😊. I created a 5h hands-on Verilog course that will save you hundreds of hours of trial-and-error and frustration so you can easily master Verilog HDL Fundamental for Digital Design and Functional Verification! 😎 Let’s go together in this adventure in the world of Digital Semiconductors and Verilog 🚀🚀🚀!

 

Design a 4bit Gray counter using Verilog

Design a 4bit Gray counter using Verilog

by | Dec 30, 2021 | Verilog Design

What you’ll learn from this easy Verilog tutorial?

Project 1:

Design using Verilog a 4bit Gray encoder, a 4bit Gray decoder and simulate a testbench for them using Modelsim Intel FPGA Edition. 

Project 2:

Design using Verilog a 4bit Gray counter, and simulate a testbench for it using Modelsim Intel FPGA Edition. 

Note: You can download the Verilog design and testbench files at the end of the article. 

Gray Codes Introduction

 These binary codes were invented by Frank Gray and are now widely used to prevent spurious (glitchy) outputs from electromechanical switches, in error correction in digital communications systems or inside digital circuits for transmitting data between blocks that operate at different clock speeds (clock domain crossing).  The codes are also called Reflected Binary codes and their special property is that two successive values differ only by 1bit. There is a very high chance that all the processors in the devices around you having this type of circuit inside because their internal blocks usually operate at different frequencies depending on their functionality.

Let’s look at the rotary position encoder from the left. It has only 1bit changing under the yellow circles. This assures that only 1bit can be misinterpreted by a reading sensor when translating from one position to another. You can read a more detailed article here. To build a Nbit Gray code is quite easy and it starts from the Nbit-1 Gray values. Let’s make a simple example for a 3bit Gray code!

  1. We first need the 2bit Gray values: 00,  01,  11,  10
  2. Next create the reflected (mirrored) values: 10,  11,  01,  00
  3. Prefix old entries with 0: 000,  001,  011,  010
  4. Prefix new entries with 1: 110,  111,  101,  100
  5. Concatenate the two sets: 000,  001,  011,  010, 110,  111,  101,  100

How to create 3bit Gray codes starting from 2bit Gray codes

Gray-to-Binary and Binary-to-Gray converters are quite easy to implement in hardware. If you want to see a detailed explanation about how this circuit is created started from the truth table, I recommend this article.

4bit Binary-to-Gray and Gray-to-Binary converters

We’ll now focus on implementing a 4bit Binary-to-Gray a Gray-to-Binary converter using Verilog and Modelsim Intel FPGA Edition.

4bit Binary-to-Gray and Gray-to-Binary converters

Watch this simple, practical video and implement the Gray encoder / decoder and a testbench for them in no time!

Download the files

Gray Counter

First In First Out (FIFO) modules are the most popular blocks used to pass data between clock domains that run at different frequencies. FIFOs have a data write and a data read port which need to communicate between them how much data there is to exchange and if the FIFO is full or empty. Gray counters are extremely useful here because a normal binary counter would create many transient (glitchy) states when the write / read pointers are passed from one clock domain to another. A normal binary counter has several bits changing between two consecutive states. If we consider the propagation delay of each bit, we can have a multitude of incorrect values of the write / read pointers that could be captured in the other clock domain. For Gray counters only one bit changes between two consecutive multi-bit values so a “wrong” binary value cannot propagate thus assuring reliable operation. Let’s implement a 4bit Gray counter and a testbench for it using Verilog and Modelsim Intel FPGA Edition!

I hope you have enjoyed this practical Verilog tutorial. If you’d like to receive more articles like this from me, I invite you joining Ovisign’s newsletter!

Where are FPGAs used?

Where are FPGAs used?

by | Dec 17, 2021 | ASIC / FPGA Generics

I bet you’ve heard a lot about FPGAs but I feel that you’ve asked yourself: “Where are these FPGAs?“, “Have I seen one until now?“, “Are you sure that there are common applications for this types of exotic chips?“.  Fact is that FPGAs are present starting from the deep bottom of the ocean (submarines) and going way far into deep space at the edge of our solar system (satellites). Let’s check out how FPGAs are used by various industries and how we silently intersect with them day-by-day.

DATA CENTERS

Chances are high that between you and reading this post a lot of FPGAs are involved in search engines, data compression, or data encryption. FPGAs are used in data centers because of their parallelism, high throughput and low-latency. Amazon WEB Services even lets yow rent FPGA fabric inside their datacenters and connect it with your application as a hardware accelerator (Amazon EC2 F1). Video processing, machine learning and data compression are just a few of possible applications that these FPGAs are used in the Amazon datacenters by their clients.

Sometimes FPGAs are used by large service providers like Google, Facebook or even banks to provide high quality data center services for a large amount of concurrent users. When 10k users search for different content in the same time, you need to have an extremely fast infrastructure that can accommodate them.

 

AUTOMOTIVE

The modern day car accommodates a large variety of chips, like microcontrollers, CPUs, GPUs and even FPGAs.  A first example for FPGA usage inside a car would be the Advanced Driver Assistance System (ADAS) which is used to give extra safety when the car is in the traffic by processing large amounts of data from various sensors (video, Lidar, pressure, temperature, motor, speed, driver gestures, etc…) and integrating them into complex algorithms to decide if the car, the driver and other traffic participants are circulating in a safe manner for everyone. An FPGA is best suited here because it can aggregate large amounts of different data types, has hundreds of I/O pins and can be reconfigured if something needs to be updated later in the production chain, or after the car is sold.

FPGAs are also used for motor control algorithms in electric / hybrid cars, in the security gateway or in the infotainment system. Since cars use so many chips the market has been highly affected by the current semiconductor crisis.

 

DEFENSE

Modern military technologies use state-of-the-art electronics devices, with high requirements for quality, safety and operating conditions. FPGAs are used for radar, sonar, electronic warfare, secure communication systems, encryption, avionics control equipment, unmanned aerial vehicles, smart munitions, etc…

The key features of an FPGA that recommends it for the defense sector are: configurability, fast IO, low latency and parallel processing power of multiple sensor sources [1].

 

 

Space

Space equipment as satellites have a lifetime of 10+ years so the chips inside them have to keep the pace with the updates of the telecom standards and algorithm updates [2]. A radiation-hardened FPGA, both by capsule materials and by the use of design techniques as Triple Module Redundancy and Hamming Codes, is a low-power reprogrammable device that can be updated with a new functionality even when the device is thousands of miles away in the harsh space environment.

The most popular applications for Space FPGA applications are: digital signal processing, high resolution optical and radar imagery, machine learning and AI [3].

 

 

Aerospace

This electronics used in this field are categorized as being safety-critical because the malfunction of even one subsystem can lead to life losses and huge material damage. Past aerial accidents related to electronic hardware lead to implementation of production safety standards for electronic airborne systems collected under the DO-254 standard. The software that operates this hardware has to be validated using the DO-178 standard.

Sometimes is easier and cheaper to validate the same behavior of a hardware circuit rather than a software implementation that should have the same behavior. All the design and verification process has to be thoroughly validated and documented using the strict procedures, sometimes taking several years.

 

 

TELECOM

Telecommunication infrastructure has to provide high-bandwidth, high-quality and high availability systems for the massive numbers of everyday users. If you’re browsing for cat videos on your phone using 5G services, there is a high chance that an FPGA is used inside a base-station to encode and decode the data transmission between your phone and the cat video server. Since there are a multitude of communications standards which are evolving once every few years, FPGAs are a perfect match for radio base stations because they can be remotely reconfigured whenever needed.

FPGAs are used to perform a wide range of fast and complex mathematical transforms (Fourier Transform, Digital Filtering, etc…) and to create custom digital signal processing chains according to every applications needs. They can offer low-power, fast-to-market, reconfigurable capabilities for any radio / wireless protocol.

 

 

HIGH-FREQUENCY TRADING

High-Frequency Trading (HFT) means to apply powerful math algorithms for stock exchange trading. The sole difference here is the astonishing speed these operations are performed which is in the nanoseconds range (1 second is 1 billion nanoseconds). In this fields the low-latency and high speed processing systems are key to large profits. While there are custom processors and servers designed specifically for this task, the low-latency and high processing power of an FPGA makes it ideal for this types of applications.

In this filed taking a decision a few tens of seconds later than your competition could mean high financial losses so taking it with a few tens of nanoseconds before you competition could result in massive profit. Another good example for FPGAs in the financial world is that JP Morgan implemented a High-Performance Computing cluster with FPGA accelerators that lets them analyze the risk of their trading transactions in near-real time.

 

ASIC PROTOTYPING

FPGA prototyping is the process of implementing/synthesizing an ASIC RTL code (Verilog or VHDL) on a physical platform that contains one or more FPGAs. These kind of platforms are used before tape out (sending the ASIC code to the factory) to check how your design responds to real-life stimulus. You can test a design with scenarios that are more complex that the ones you have simulated at RTL level. For example for, some protocols, simulating a 1ms of traffic using Modelsim (or other simulator) could take 2h, but on a real-life platform it will take 1ms. With these platforms you can find bugs that would occur only in heavy-duty real-life testing conditions.

Another role of these platforms is to start firmware development for the final chip way before the chip is mass produced. Since this is usually done by another department than the ones developing the chip, it bring a huge advantage in reducing overall costs and development time.

These development boards usually have multiple FPGAs, each having millions of logic cells (billions of transistors), with a total cost of hundreds of thousands of dollars. Even so their overall use brings costs reductions of millions if they are used efficiently.

CRYPTOCURRENCY MINING

Because of the cryptocurrency revolution and blockchain hype people tried to find ways to mine these cryptocurrencies in a energy-efficient manner on devices that bring the maximum performance. Mining cryptocurrency means to find a solution to a complex mathematical problem and present it to a network before the other members. Initially this was done using your processor, but this was consuming lots of time and was not energy-efficient. The next step was to design ASICs that were extremely fast, but as the number o cryptocurrencies expanded, and the initial ones having algorithm updates, the equipment developers migrated towards GPUs and FPGAs. While GPUs are more power hungry and harder to find in stocks than an FPGA, this gives FPGAs a great profitability advantage over others kinds of chips.

This  brought massive media exposure for FPGAs, gave them a piece of the hype the crypto stage is enjoying, and attracted development talent from other areas to FPGAs. FPGA mining is still a niche area in crypto mining because the mining workflow is considered to be extremely complex compared to ASIC / GPU mining.

 

WANT TO LEARN FPGA DESIGN?

As you can see there are many interesting high-tech fields where FPGAs are deployed and having a job there means and a wonderful career full of challenges and accomplishments, that also offers financial stability. The FPGA market is expected to grow with almost 10% per year until 2027 so there is a high need for professionals to fill these high-end jobs.

Working in FPGA design and verification is somehow similar to academic research and it involves a great imagination an creative problem-solving abilities. FPGAs are usually “programmed” using Hardware Description Languages and the one this blog is specialized is called Verilog HDL. FPGA design and Verilog as marketed as “difficult to learn”, or “complex”, but remember that it is NOT rocket science…

I had the same kind of problem when I started with FPGAs more 12 years ago and I had some hard times because I didn’t knew the technology, nor how a hardware description language works and how to code with it… I lost hundreds and hundreds of hours just to learn what I shouldn’t do… After a 10 years career in ASIC / FPGA design and verification plus a Ph.D in designing FPGA accelerators, I built this simple, hand-on tool that will help you master the secrets of Verilog very fast. If you are interested learning Verilog in a easy way, you can read more here….

 

Types of FPGA architectures

Types of FPGA architectures

by | Dec 12, 2021 | ASIC / FPGA Generics

Field Programmable Gate Arrays (FPGAs)  are general-use, reconfigurable chips that are used for a particular workload or for ASIC prototyping. An FPGA allows massive data parallelism and can achieve speed and energy consumption improvements in orders of magnitude compared with a generic processor.  They are very popular in video processing, digital signal processing, cryptography, data compression, machine learning and AI, auto, aerospace and military applications. An FPGA can be programmed multiple times until the desired functionality for a circuit is obtained or it can updated even if a bug is found later in the production stages. ASICs don’t have this kind of flexibility and bugs found in production may sometimes be catastrophic for the chip’s functionality. FPGAs are composed of configurable logic blocks or CLB (contains look-up tables, combinational logic and flip-fops), programmable interconnects (interconnects + switch matrix), and I/O pads. To “program” an FPGA means to emulate the functionality of a digital circuit using the FPGA fabric. This is usually achieved by using a Hardware Description Language like Verilog or VHDL. The Synthesis tool will map the circuit to the existing FPGA configurable logic and will use the programmable interconnects to connect these blocks between them. The FPGA is configured by downloading a bitstream inside it and the 1/0 bits will enable or disable the functionality of the CLBs and of the interconnects.

 

Types of FPGA

If we analyze the internal structure of an FPGA we have three categories: Symmetrical Arrays, Row-based architecture, and Hierarchical PLDs.

 

Symmetrical Arrays FPGAs

 

This architecture consists of a rectangular array of logic blocks separated by channels containing routing resources (interconnects + switches). These blocks can be programmed to implement any desired function and are connected with the outside environment by using the I/O blocks. The function of the I/O blocks are used for tri-state control, output transition speed, pullp-up ori pull-down. The fastest interconnection is between adjacent blocks while the delay increases with the distance between the CLBs.

Row-based architecture

 

The CLBs are grouped in rows with programmable interconnects placed between them. The I/O blocks are at the edge of the structure. Complex circuits are emulated by connecting adjacent rows via vertical interconnects.

 

 

Hierarchical PLDs

Hierarchical PLDs have a more complex layout. The top level is composed of logic blocks and interconnects. The logic blocks contain logic modules, which have combinatorial and sequential functional elements. The functional elements are controlled by the configuration bitstream stored inside the FPGA. The I/O blocks are placed at the edge of the system, shrouding the logic blocks and the interconnects.

FPGA programming technologies

Since the FPGA fabric is reconfigurable it needs a storage mechanism for the bitstream that will enable / disable the configurable logic and the programmable switches. There are three main technologies:

  1. SRAM-based FPGAs: When the power source is turn on static RAM cells are loaded with the bitstream value. The FPGA requires an external flash memory for storing the bitstream while the power is OFF. The FPGA loses its configuration each time the power is shut down returning to its unconfigured state (volatility).
  2. Antifuse-based FPGAs: This makes the FPGA one-time programmable because a fuse is burnt when the bitstream is loaded. This makes the FPGA non-reprogrammable but the advantage is that it will retain the functionality even with no power.
  3. Flash-based FPGAs: The FPGA has internal FLASH memory to retain the configuration when powered down. This eliminates the need for an external memory and the device can be reprogrammed while the FLASH cells are functional.

Modern FPGAs

Cyclone V FPGA (source)

Modern FPGAs are composed of Adaptive Logic Modules (ALM) and Logic Elements (LEs) connected using programmable interconnects. Besides the ALMs and LEs a modern FPGA may have a processor core (like the Xilinx Zynq family), Transceivers, Hard IP blocks like PCIe, dedicated Digital signal Processing engines, and even analog modules like programmable PLLs (Phase Locked Loop – used to generate clock signal), and integrated Analog-to-Digital Converters (XADC from Xilinx)

Why use an FPGA?

It is a very cheap solution for prototyping and also for low-volume flexible products. In terms of costs FPGAs vary from tens of dollars to thousands of dollars and you always must select one that fits the throughput and financial budget of your system. The same RTL code (Verilog or VHDL) can be implemented in an ASIC if needed later, and it is an important for measuring the performance of a specific circuit. For example companies that sell soft cores (Intellectual Property or IP) use FPGAs to profile the performance of their circuits in terms of maximum frequency, power, consumed logic gates and throughput. FPGAs are also a great solution as accelerators in heterogeneous systems where a standard low-power CPU is used to control a system and the FPGA is used to process compute intensive payloads while the CPU is idle or performs other task (video, encryption, etc…).

Is it hard to become an FPGA designer?

Most posts on the Internet promote that it is very hard to understand Hardware Description Languages (like Verilog) that’s why many engineering students choose other niches to work after they finish their faculty. If I look back at my journey the hardest part about Verilog and FPGAs was the fact that I wasn’t aware about what I was doing. The most challenging part was to know how to code synthesizable designs for FPGA using Verilog. If you’re a beginner (you don’t have high speed / large area / complex designs) a good path to follow would be to first understand how Verilog HDL code works for Digital Circuits Design and Functional Verification, and your FPGA journey will become much easier. I had the same problem for years and faced much bigger challenges that I should of because I didn’t knew back then how important is to understand the correspondence between Verilog code and actual digital circuits. Another thing that I didn’t had were some clear practical steps to develop my skills in Verilog… After 10 years of industry experience and a Ph.D involving FPGAs and Verilog, I developed a simple practical tool that will help you easily master Verilog HDL. It contains all things I wished I’d knew when I started my journey 10 years ago.  Find out more…

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